Conventional integrated circuits tend to be composed of devices from the same semiconductor family. In many cases, the active components of the devices are made from the same epitaxially-deposited layers. In some cases of heterogeneous integrated circuits, the integration of the dissimilar semiconductor devices is performed off-chip as part of packaging, rather than as part of the integrated circuit fabrication. One reason is that the size of the devices precludes direct mechanical manipulation. As a result, the scale of integration that can be achieved with the off-chip approach is reduced due to the decreased density of the heterogeneous circuit elements as compared to on-chip integration. In addition, achieving interconnection speeds comparable to those speeds that can be achieved when integration is performed through an on-chip fabrication process can be extremely difficult.
In other heterogeneous integrated circuits, dissimilar semiconductor devices are integrated by growing the device material layers on top of one another. This approach is limited to device materials that are compatible to epitaxial overgrowth otherwise high defect levels lead to poor material quality and device performance. In addition, even for epitaxial compatible device materials, this approach tends to result in topology problems leading to degradation in material quality as the thickness of the layers increases. Uneven device heights complicate interconnections because interconnection with metal layers works best when the metal layer is deposited on a planar surface. In addition, inactive device layers below or above an active device impede thermal conduction of generated waste heat and can also have a deleterious effect on device performance due to parasitics.
One exemplary prior art technique of integrating heterogeneous devices at the transistor or device level illustrates the interconnection and thermal problems associated with the prior art technique. In this technique, epitaxially grown devices are built on a first growth substrate. Other epitaxial device layers are grown on a second growth substrate in such a way that an inverted stack of device layers can be bonded on top of the devices on the first growth substrate by essentially flipping the second growth substrate over and sandwiching the device with the added epitaxial layers between the first and second growth substrates. The second growth substrate is removed to expose the added epitaxial device layers. The next step would be to process the epitaxial layers into the other desired devices. This may result in some devices on the first growth substrate having an epitaxially grown other device bonded on top and some devices that do not. A thermal problem arises in that the heat from an epitaxially grown other device has to pass through the device below before it can be dissipated through the substrate.
Furthermore, the interconnection problem arises because in processing the epitaxially grown layers on top of the devices, some devices may be intentionally left without an epitaxially grown device on top. The result is an uneven surface that has to be planarized before interconnections can be made. An essential step in the planarization process is to etch or drill via holes through the planarization layer that allows interconnection to the devices. However, these planarization steps increase the complexity and cost of fabrication and the chances of failure.
Another exemplary prior art technique of integrating heterogeneous devices at the transistor or device level to build a heterogeneous integrated circuit further illustrates the thermal problems associated with the prior art technique. According to this technique, epitaxial grown devices are built on a first growth substrate. In the device building process, various planarization layers are incorporated around the device structures to facilitate electrical contacts to the active device regions (i.e. emitter, base, collector) and for interconnecting different devices into circuit elements. Other epitaxial device layers are grown on a second growth substrate in such a way that an inverted stack of device layers can be bonded on top of the devices built on the first growth substrate. The bonding process essentially flips the inverted epitaxial layers and sandwiches the devices of the first substrate and the flipped epitaxial devices layers between the first and second growth substrates. Next, the second growth substrate is removed revealing the bottom of the flipped epitaxial device layers. The epitaxial device layers in this configuration are in a normal orientation (i.e. emitter up). In the next step, a second set of devices is built from the flipped epitaxial device layers. In the device building process, various planarization layers are incorporated around the device structures to facilitate electrical contacts to the active device regions (i.e. emitter, base, collector) and for interconnecting devices from the first and second sets of devices into a heterogeneous integrated circuit. This results in devices from the second epitaxial layers to be position on top of devices from the first epitaxial layers or on planarization layers. A thermal problem arises in that heat from the second epitaxial grown devices must pass through the first epitaxial grown devices or planarization layers before it can be dissipated through the substrate.
Therefore, new methods of fabrication of heterogeneous integration circuits, and corresponding devices, are desired that minimize interconnection problems and maintain desirable thermal properties.